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Online Open QUIZ (MCQs) on Pulse and Digital Circuits (PDC)


LINEAR WAVE SHAPING : High  pass and low pass  RC circuits and their response for  sinusoidal, step,  pulse, square wave, ramp and Exponential inputs, RC network as a differentiator and integrator, attenuators and its applications in CRO probe, RL and RLC circuits and their response to step input, ringing circuit.
Important Points to REMEMBER:
A linear circuit is one which consists of only linear elements. Examples of Linear elements are R, L and C.

A Non-Linear network is one which should at least contain one non-linear element, along with linear elements. Examples of non-linear elements are Diode, BJT, FET, SCR, UJT, DIAC, TRIAC etc...

Response of Linear Networks :
A linear network can be applied with sinusoidal or non-sinusoidal input.
If a sinusoidal input is applied to a linear network, then the response (output) of the network is also sinusoidal except a change in magnitude and/or phase in the output waveform. ie. Linear circuit does not alter the shape of sinusoidal input signal.
When a non-sinusoidal signal is applied to a linear network, then output will be distorted ie. Output signal is different from input signal.
Examples of Non-sinusoidal signals are Impulse, Step, Pulse, Square, Ramp, Exponential etc....

Def : Linear Wave Shaping : is the study of variation in output signal of linear network, when applied with non-sinusoidal signals.

The function of capacitor is to store energy in the form of electric field, which is proportional to voltage. In general, capacitor charges when a current flows into it and while capacitor discharges, current flows out of the capacitor.
When a DC or step voltage is applied, capacitor charges exponentially to the final value from initial value based time constant of the circuit.

Time constant (τ) is the product of equivalent resistance and equivalent capacitance across the terminals of interest (τ = RC). Units of time constant are seconds.
In one time constant of time, capacitor either charges / discharges to 63.2% of the final value. Capacitor requires a minimum of five time constants of time to charge / discharge to the final value. Hence small the time constant , faster the response of the circuit.

Risetime (tr) : is the time required for the waveform to reach from 10% to 90% of its final value. Rise time for a simple RC circuit is equal to 2.2RC.
LPRC circuit works as Low Pass Filter, which passes all the frequencies starting from DC (0 Hz) to upper 3dB frequency (fH). Bandwidth of LPRC circuit is equal to fH.
Bandwidth and rise time are related as BW * tr = 0.35

LPRC circuit works as integrator if time constant of the circuit is very large compared to duration of the pulse.
For Integrator, if the input is Impulse then the output is Step (or) if the input is step then the output is Ramp (or) if the input is Ramp then the output wave shape is parabola.

Video Solutions to GATE 2015 ECE Question Paper - Analog Circuits (Electronic Circuit Analysis)

GATE 2015 ECE – Questions on Analog Circuits with Answers

   1.       In the circuit shown, assume OP-AMP is ideal then the 3 dB cut off frequency (in Hz) is __________

   2.       Consider the bode plot shown in figure. Assume that all the poles and zeros are real valued. The value of fH – fL (in Hz) is _____________

   3.       At very high frequencies, the peak output voltage Vo (in volts) is ______________

   4.       In the circuit shown, assume that the OP-AMP is ideal. If the gain (Vo/Vin) is –12 , then the value of R (in kΩ) is _________________

   5.       Negative feedback in a closed loop control system DOES NOT
a.       Reduce the overall gain
b.      Reduce  bandwidth
c.       Improve disturbance rejection
d.      Reduce sensitivity to parameter variation 

   6.       In the circuit shown, assume that the OP-AMP is ideal. The bridge output voltage Vo (in mV) for δ = 0.05 is _______________

   7.       The circuit shown in the figure has an ideal OP-AMP. The oscillation frequency and the condition to sustain the oscillations respectively are ________________

   8.       In the circuit shown, I1 = 80 mA and I2 = 4 mA. Transistors T1 and T2 are identical. Assume that thermal voltage is 26 mV at 27oC. At 50oC, the value of voltage V12 = V1 – V2 (in mV) is _______________

   9.       In the circuit shown, Vo = VOA for switch SW in position A and Vo = VOB for switch SW in position B. Assume that the OP-AMP is ideal. The value of VOB/VOA is ______________

   10.   If the circuit shown has to function as a clamping circuit, then which one of the following conditions should be satisfied for the sinusoidal signal of period T?

   11.   In the bistable circuit shown, the ideal OP-AMP ahs saturation levels of ± 5 volts. The value of R1 (in kΩ) that gives a hysteresis width of 500 mV is _________________

   12.   In the ac equivalent circuit shown, the two BJTs are biased in active region and have identical parameters with β>>1. The open circuit small signal voltage gain is approximately is _________________

    13.   Assuming that the OP-AMP in the circuit shown is ideal, the output voltage Vo (inn volts) is __________

   14.   For the voltage regulator circuit shown,the input voltage (Vin) is 20 V ± 20% and the regulated output voltage (Vout) is 10 volts. Assume the OP-AMP is ideal. For a load RL drawing 200 mA, the maximum power dissipation in Q1 (in Watts) is _________________


Video Solutions to GATE 2015 ECE Question Paper - Digital Circuits (Digital Electronics) (STLD)

GATE 2015 ECE – Questions on Digital Circuits with Solutions

    1.       The circuit shown consists of JK flip flops, each with an active LOW asynchronous reset. The counter corresponding to this circuit is ___________
a.       Mod – 5 binary UP counter 
b.      Mod – 6 binary DOWN counter
c.       Mod – 5 binary DOWN counter
d.      Mod – 6 binary UP counter
    2.       In the circuit shown, D1, D2 and D3 are ideal and inputs E1, E2 and E3 are 0 volts for logic’0’ and 10 volts for logic ‘1’. What logic gate does the circuit represent?
a.       3 input OR gate
b.      3 input NOR gate
c.       3 input AND gate
d.      3 input XOR gate
   3.       A universal gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown.
Which one of the following statements is TRUE?
a.       Gate 1 is universal gate 
b.      Gate 2 is universal gate
c.       Gate 3 is universal gate
d.      None of the gates shown is universal gate
   4.       A three bit pseudo random number generator is shown. Initially the value of output Y = Y2Y1Y0 is set to 111. The value of output Y after three clock cycles is _________
a.       000
b.      001
c.       010
d.      100
   5.       An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing
a.       NOR gates to NAND gates
b.      Inverters to Buffers
c.       NOR gates to NAND gates and inverters to buffers
d.      5 volts to ground
   6.       Consider a four bit Digital to Analog converter. The analog value corresponding to a digital signals of values 0000 and 0001 are 0 volts and 0.0625 volts respectively. The analog value (in volts) corresponding to the digital signal 1111 is ______________
   7.       In a 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are respectively
a.       B and F
b.      A and F
c.       H and F
d.      A and C
   8.       A 16 KB memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ______________
   9.       A 3 input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca. Which one of the following gate is represented by the function M(M’(a,b,c),M(a,b,c’),c)?
a.       3 input NAND gate
b.      3 input XOR gate
c.       3 input NOR gate
d.      3 input XNOR gate
   10.   The Boolean expression F(x,y,z) = x’yz’+xy’z’+xyz’+xyz converted into canonical product of sum (POS) form is ___________
   11.   All the logic gates shown in the figure have a propagation delay of 20 ns. Let A=C=0 and B=1 until time t = 0. At t = 0, all the inputs flip (i.e. A=C=1 and B=0) and remain in that state. For t>0, output z=1 for a duration (in 20 ns) of____________
   12.   A Mod-N counter using a synchronous binary UP counter with asynchronous clear input is shown in the figure. The value of N is_______________

   13.   In the figure shown, the output Y is required to be Y = AB+C’D’. The gates G1 and G2 must be _____
a.       NOR, OR
b.      OR, NAND
c.       NAND, OR
d.      AND, NAND
   14.   In an 8085 microprocessor, which one of the following instructions changes the content of the accumulator?
a.       MOV  B,M
b.      PCHL
c.       RNZ
d.      SBI BEH    .
   15.   A function of Boolean variables X,Y and Z is expressed in terms of the min-terms as F(X,Y,Z) = m(1,2,5,6,7). Which one of the product of sums given below is equal to the given function?
    16.   The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a _______________
a.       Mod – 2 counter  
b.      Mod – 4 counter
c.       Mod – 5 counter
d.      Mod – 6 counter 
   17.   Problem on Design of 1 to 8 De-multiplexer using two 2 to 4 decoders with extra logic gates.