**Video Lecture Series from IIT Professors :****VLSI Broadband Communication Circuits**

**by Prof.Nagendra Krishnapura sir**

###
*Dr. Nagendra Krishnapura*

He is an associate professor in the VLSI group of the department of Electrical Engineering of the Indian Institute of Technology, Madras. He work in the area of analog and mixed signal circuits and signal processing.
*Dr. Nagendra Krishnapura*

He graduated with a Ph.D. from Columbia University, New York in Oct. 2000. He worked at the Columbia Integrated Systems Laboratory under the guidance of Prof. Yannis Tsividis in the area of nonlinear analog signal processing for low power integrated circuits. He obtained his B. Tech. degree in electronics and communications engineering from the Indian Institute of Technology, Madras, in 1996. Between 2000 and 2005, He worked as a senior design engineer at Celight, Inc. and Multilink(later Vitesse Semiconductor) where he designed integrated circuits for high speed communications. From 2003 to 2005, he was an Adjunct Assistant Professor and taught courses on Analog Circuit Design at Columbia University.

1. Introduction to broadband digital communication

2. Introduction to broadband digital communication

3. Serializers and deserializers

4. lecture - 4

5. CMOS logic, single ended data transmission, limitations

6. Current mode logic-basic circuit design

7. Current mode logic-MUX, XOR, latch

8. Current mode logic-latch design

9. Current mode logic-latch characteristics

10. Low pass transmission channel-Intersymbol interference, error rate

11. First order channel model, ISI

12. ISI, jitter, eye opening

13. Channel characteristics-Intersymbol interference, Crosstalk

14. Equalizer design

15. Equalizer design-minimizing the residual error

16. Equalization-Effect on noise and crosstalk

17. Tradeoffs between equalization at Tx and Rx; Design of Tx equalizers

18. Design of Transmit equalizers using flip-flops and transconductors

19. Tx equalizer-design considerations

20. Tx equalizer-design considerations; realizing variable coefficients

21. Differential pair-effect of tail node capacitance; Continuous time equalization

22. Continuous-time equalizer realization; replica biasing for the tail current source

23. Assignment 2 discussion

24. Replica biasing, optimizing transmitter swing

25. Replica biasing, optimizing transmitter swing

26. Analog layout optimization; Equalization at the receiver

27. Equalization at the receiver; Basics of adaptation

28. LMS adaptation

29. Sign-sign LMS adaptation

30. LMS implementation details

31. Adaptive equalizer implementation, S/H based equalizer, obtaining the gradients

32. Mid term discussion; Multiplexed and demultiplexed PRBS sequences; Latch vs. amplifier; Zeros for pre- and post- cursor equalization; Echo cancellation

33. Decision feedback equalizers-elimination of noise enhancement; Error propagation

34. Decision feedback equalizers-bit error rate

35. Decision feedback equalizers-implementation issues

36. Assignment 3 discussion

37. Decision feedback equalizers-implementation issues

38. Introduction to clock and data recovery-Frequency multiplication using a phase locked loop

39. Type I PLL; derivation of the phase model of the PLL; Tri state phase detector

40. (continued) Type I PLL; derivation of the phase model of the PLL; Tri state phase detector

41. Type I PLL; Reference feedthrough; Tradeoff between reference feedthrough and lock range

42. Stability of feedback loops; Derivation of the type II PLL

43. Realization of type II PLLs-charge pump, loop filter

44. Reference feedthrough in a type II PLL; Phase detector for random data

45. Linear phase detector for random data

46. Linear phase detector; Transfer functions in a PLL

47. PLL review

48. Binary phase detectors; bang bang jitter

49. Miscellaneous topics-Optimal equalizers; Linearity assumption of PLL model; PLL capture phenomenon; Hogge phase detector offset correction

1. Introduction to broadband digital communication

2. Introduction to broadband digital communication

3. Serializers and deserializers

4. lecture - 4

5. CMOS logic, single ended data transmission, limitations

6. Current mode logic-basic circuit design

7. Current mode logic-MUX, XOR, latch

8. Current mode logic-latch design

9. Current mode logic-latch characteristics

10. Low pass transmission channel-Intersymbol interference, error rate

11. First order channel model, ISI

12. ISI, jitter, eye opening

13. Channel characteristics-Intersymbol interference, Crosstalk

14. Equalizer design

15. Equalizer design-minimizing the residual error

16. Equalization-Effect on noise and crosstalk

17. Tradeoffs between equalization at Tx and Rx; Design of Tx equalizers

18. Design of Transmit equalizers using flip-flops and transconductors

19. Tx equalizer-design considerations

20. Tx equalizer-design considerations; realizing variable coefficients

21. Differential pair-effect of tail node capacitance; Continuous time equalization

22. Continuous-time equalizer realization; replica biasing for the tail current source

23. Assignment 2 discussion

24. Replica biasing, optimizing transmitter swing

25. Replica biasing, optimizing transmitter swing

26. Analog layout optimization; Equalization at the receiver

27. Equalization at the receiver; Basics of adaptation

28. LMS adaptation

29. Sign-sign LMS adaptation

30. LMS implementation details

31. Adaptive equalizer implementation, S/H based equalizer, obtaining the gradients

32. Mid term discussion; Multiplexed and demultiplexed PRBS sequences; Latch vs. amplifier; Zeros for pre- and post- cursor equalization; Echo cancellation

33. Decision feedback equalizers-elimination of noise enhancement; Error propagation

34. Decision feedback equalizers-bit error rate

35. Decision feedback equalizers-implementation issues

36. Assignment 3 discussion

37. Decision feedback equalizers-implementation issues

38. Introduction to clock and data recovery-Frequency multiplication using a phase locked loop

39. Type I PLL; derivation of the phase model of the PLL; Tri state phase detector

40. (continued) Type I PLL; derivation of the phase model of the PLL; Tri state phase detector

41. Type I PLL; Reference feedthrough; Tradeoff between reference feedthrough and lock range

42. Stability of feedback loops; Derivation of the type II PLL

43. Realization of type II PLLs-charge pump, loop filter

44. Reference feedthrough in a type II PLL; Phase detector for random data

45. Linear phase detector for random data

46. Linear phase detector; Transfer functions in a PLL

47. PLL review

48. Binary phase detectors; bang bang jitter

49. Miscellaneous topics-Optimal equalizers; Linearity assumption of PLL model; PLL capture phenomenon; Hogge phase detector offset correction