Video Lecture Series from IIT Professors :CMOS Mixed Signal VLSI Design by Prof. Maryam S. Baghini, and Prof. Dinesh Sharma
Prof. Maryam Shojaei Baghini
|Department of Electrical Engineering|
|Mumbai 400 076, India.|
- Post Doc. Research (Dept. of Electrical Engineering, IIT-Bombay)
- Ph.D. and M.S., both in Electrical Engineering (Major: Electronics), Sharif Univ. of Technology
- B. S., Electrical Engineering (Major: Electronics), S. B. Univ. of Kerman
Video lectures on "CMOS Mixed Signal VLSI Design" by Prof. Maryam Shojaei Baghini, and Prof. Dinesh Sharma , IIT Bombay.
1. Introduction to CAD tools and Technology and modern network synthesis theory
2. Ultra Dynamic Voltage Scaling : Error Resiliency, Power dissipation and Reliability
3. Design of Continuous Time Filters (part 1) - design and synthesis of ladder filters - frequency transformation - signal flow graph
4. Design of Continuous Time Filters (part 1) Continued....
5. Design of Continuous Time Filters (part 2) - Integrator based realization of ladder filters - Frequency transformation - time domain performance - effect of nonidealities
6. Sampled Data Filters (Part 1) - basics of sampled data systems - discrete time frequency transformations - basics of switched capacitor filters
7. Sampled Data Filters (part 2)
8. Introduction to Switched Capacitor Filters
9. Data Converters
10. Design of Switched Capacitor Filters - Design example - signal flow graph and differential architecture - commercial switched capacitor filter in PSoC.
11. Design of Switched Capacitor Filters Continued...
12. Data Converters - performance specifications - ADC and DAC architectures - Flash ADC
13. Design of High data rate sigma delta ADC
14. Floor Planning - power supply and grounding - Guard rings and shielding
15. Introduction to Phase Locked Loop (PLL)
16. Dynamic of Phase Locked Loop (PLL)
17. DAC (Digital to Analog Converters)
18. SAR ADC using parallel charge based DAC and Pipeline ADC
19. PLL non idealities , design considerations, estimation of capture range and lock range
20. Delay Locked Loop (DLL)
21. Examples of Pipeline ADC and Successive Approximation Register (SAR) ADC
22. Examples on Multi Phases
23. PLL (Phase Locked Loop) (part 2) - XOR gate as digital phase detector - Basics of PLL dynamics - False Locking - Digital Phase & frequency detector
25. PLL (part 4)
26. PLL (part 5) and DLL