Video Lectures on "Digital System design with PLDs and FPGAs" by Prof. Kuruvilla Varghese, IISc Bangalore

Video Lecture Series from IIT Professors :

Digital System design with PLDs and FPGAs by Prof. Kuruvilla Varghese sir

Prof. Kuruvilla Varghese

Principal Research Scientist
DESE, Indian Institute of Science, Bangalore 560012
Tel: +91 80 2293 3092
E-mail: edkuru@dese.iisc.ernet.in

COURSE OUTLINE

Design:   Hierarchy, controller (FSM), case study, meta-stability, synchronization, FSM issues, timing issues, pipelining, resource sharing.

VHDL:   Different models, simulation  cycles, process, concurrent and sequential statements,  loops,   delay   models,   library   packages, functions,   procedures, synthesis, test bench.

PLD:   SPLD and CPLD architecture, timing, applications.

F P G A : Logic   block   and   routing   architecture,   Virtex-II,   Stratix architectures, constraints, STA, case study.

Hardware-software co-simulation, bus function models, SoPC.

 References :
 
 1. Jon F Wakerl y, Di gi tal  Desi gn: Pri nci pl es and Practi ces, Prenti ce Hal l .
 2. Kevi n Skahi l , VHDL for programmabl e l ogi c, Addi son Wesl ey.
 3. Zai nal abedi n Navabi , VHDL, anal ysi s and model i ng of di gi tal  systems, McGraw-Hi l l .
 4. PLD, FPGA data sheets.

Mod-01 Lec-01 Course Contents, Objective

Mod-01 Lec-02 Revision of Prerequisite

Mod-01 Lec-03 Design of Synchronous Sequential Circuits

Mod-02 Lec-04 Analysis of Synchronous Sequential Circuits

Mod-02 Lec-05 Top-down Design

Mod-02 Lec-06 Controller Design

Mod-02 Lec-07 Control algorithm and State diagram

Mod-02 Lec-08 Case study 1

Mod-03 Lec-09 Entity, Architecture and Operators

Mod-03 Lec-10 Concurrency, Data flow and Behavioural models

Mod-03 Lec-11 Structural Model, Simulation

Mod-03 Lec-12 Simulating Concurrency

Mod-03 Lec-13 Classes and Data types

Mod-03 Lec-14 Concurrent statements and Sequential statements

Mod-03 Lec-15 Sequential statements and Loops

Mod-03 Lec-16 Modelling flip-flops, Registers

Mod-03 Lec-17 Synthesis of Sequential circuits

Mod-03 Lec-18 Libraries and Packages

Mod-03 Lec-19 Operators, Delay modelling

Mod-03 Lec-20 Delay modelling

Mod-03 Lec-21 VHDL Examples

Mod-04 Lec-22 VHDL Examples, FSM Clock

Mod-04 Lec-23 FSM issues 1

Mod-04 Lec-24 FSM Issues 2

Mod-04 Lec-25 FSM Issues 3

Mod-04 Lec-26 VHDL coding of FSM

Mod-04 Lec-27 FSM Issues 4

Mod-04 Lec-28 FSM Issues 5

Mod-04 Lec-29 Synchronization 1

Mod-04 Lec-30 Synchronization 2

Mod-05 Lec-31 Evolution of PLDs

Mod-05 Lec-32 Simple PLDs

Mod-05 Lec-33 Simple PLDs: Fitting

Mod-05 Lec-34 Complex PLDs

Mod-06 Lec-35 FPGA Introduction

Mod-06 Lec-36 FPGA Interconnection, Design Methodology

Mod-06 Lec-37 Xilinx Virtex FPGA’s CLB

Mod-06 Lec-38 Xilinx Virtex Resource Mapping, IO Block

Mod-06 Lec-39 Xilinx Virtex Clock Tree

Mod-06 Lec-40 FPGA Configuration

Mod-06 Lec-41 Altera and Actel FPGAs

Mod-06 Lec-42 VHDL Test bench

Mod-06 Lec-43 Case study 2

Mod-06 Lec-44 Case study on FPGA Board