SECTION 11. l: 8051 INTERRUPTS
1. Of the interrupt and polling methods, which one avoids tying down the microcontroller?
2. Besides reset, how many interrupts do we have in the 8051?
3. In the 8051, what memory area is assigned to the interrupt vector table? Can the programmer change the memory space assigned to the table?
4. What are the contents of register IE upon reset, and what do these contents mean?
5. Show the instruction to enable the EX0 and Timer 0 interrupts.
6. Which pin of the 8051 is assigned to the external hardware interrupt INTl?
7. What address in the interrupt vector table is assigned to the INTl and Timer 1 interrupts?
3. Address locations 0000 to 25H. No. They are set when the processor is designed.
4. All Os means that all interrupts are masked, and as a result no interrupts will be responded to by the 8051.
5. MOV IE, #10000011B
6. P3.3, which is pin 13 on the 40-pin DIP package
7. 0013H for INTl and OOlBH for Timer 1
SECTION 11.2: PROGRAMMING TIMER INTERRUPTS
1. True or false. There is only a single interrupt in the interrupt vector table assigned to both Timer 0 and Timer 1.
2. What address in the interrupt vector table is assigned to Timer 0?
3. Which bit of IE belongs to the timer interrupt? Show how both are enabled.
4. Assume that Timer 1 is programmed in mode 2, THl = F5H, and the IE bit for Timer 1 is enabled. Explain how the interrupt for the timer works.
5. True or false. The last two instructions of the ISR for Timer 0 are:
1. False. There is an interrupt for each of the timers, Timer O and Timer 1.
3. Bits Dl and 03 and "MOV IE, # 1 o o o 1 o 1 o B" will enable both of the timer interrupts.
4. After Timer 1 is started with instruction "SETB TRl", the timer will count up from F5H to FFH on its own while the 8051 is executing other tasks. Upon rolling over from FFH to 00, the TFl flag is raised, which will interrupt the8051 in whatever it is doing and force it to jump to memory location 00lBH to execute the ISR belonging to this interrupt.
5. False. There is no need for "CLR TF0" since the RETI instruction does that for us.
SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
1. True or false. There is a single interrupt in the interrupt vector table assigned to both external hardware interrupts
IT0 and ITl.
2. What address in the interrupt vector table is assigned to INT0 and INTl? How about the pin numbers on port 3?
3. Which bit of IE belongs to the external hardware interrupts? Show how both are enabled.
4. Assume that the IE bit for the external hardware interrupt EXl is enabled and is active low. Explain how this interrupt works when it is activated.
5. True or false. Upon reset, the external hardware interrupt is low-level triggered.
6. In Question 5, how do we make sure that a single interrupt is not recognized as multiple interrupts?
7. True or false. The last two instructions of the ISR for INT0 are:
8. Explain the role that each of the two bits TCON.0 and TCON.2 play in the execution of external interrupt 0.
1. False. There is an interrupt for each of the external hardware interrupts of INT0 and INTl.
2. 0003H and 0013H. The pins numbered 12 (P3.2) and 13 (P3.3) on the DIP package.
3. Bits D0 and D2 and "MOV IE, #10000101B" will enable both of the external hardware interrupts.
4. Upon application of a low pulse (4 machine cycles wide) to pin P3.3, the 8051 is interrupted in whatever it is doing and jumps to ROM location 0013H to execute the ISR.
6. Make sure that the low pulse applied to pin INTl is no wider than 4 machine cycles. Or, make sure that the INTl pin is brought back to high by the time the 8051 executes the RETI instruction in the ISR.
7. False. There is no need for the "CLR TCON. 0" since the RETI instruction does that for us.
8. TCON.0 is set to high to make INTO an edge-triggered interrupt. If INT0 is edge-triggered (that is, TCON.0 is set), whenever a high-to-low pulse is applied to the INTO pin it is captured (latched) and kept by the TCON.2 bit by making TCON.2 high. While the ISR for INT0 is being serviced, TCON.2 stays high no matter how many times an H-to-L pulse is applied to pin INT0. Upon the execution of the last instruction of the ISR, which is RETI, the TCON.2 bit is cleared, indicating that the INTO pin can respond to another interrupt.
SECTION 11.4: PROGRAMMING THE SERIAL COMMUNICATION INTERRUPT
1. True or false. There is a single interrupt in the interrupt vector table assigned to both the TI and RI interrupts.
2. What address in the interrupt vector table is assigned to the serial interrupt?
3. Which bit of the IE register belongs to the serial interrupt? Show how it is enabled.
4. Assume that the IE bit for the serial interrupt is enabled. Explain how this interrupt gets activated and also explain its actions upon activation.
5. True or false. Upon reset, the serial interrupt is active and ready to go.
6. True or false. The last two instructions of the ISR for the receive interrupt are:
7. Answer Question 6 for the send interrupt.
1. True. There is only one interrupt for both the transfer and receive.
3. Bit D4 (IE.4) and "MOV IE, # 10010000B" will enable the serial interrupt.
4. The RI (received interrupt) flag is raised when the entire frame of data, including the stop bit, is received. As a result the received byte is delivered to the SBUF register and the 8051 jumps to memory location 0023H to execute the ISR belonging to this interrupt. In the serial COM interrupt service routine, we must save the SBUF contents before it is lost by the incoming data.
6. True. We must do it since the RETI instruction will not do it for the serial interrupt.
7. CLR TI
SECTION 11.5: INTERRUPT PRIORITY IN THE 8051/52
1. True or false. Upon reset, all interrupts have the same priority.
2. What register keeps track of interrupt priority in the 8051? Is it a bit-addressable register?
3. Which bit of IP belongs to the serial interrupt priority? Show how to assign it the highest priority.
4. Assume that the IP register contains all Os. Explain what happens if both INT0 and INTl are activated at the same time.
5. Explain what happens if a higher-priority interrupt is activated while the 8051 is serving a lower-priority interrupt (that is, executing a lower-priority ISR).
1. False. They are assigned priority according to Table 11-3.
2. IP (interrupt priority) register. Yes, it is bit-addressable.
3. Bit D4 (IP.4) and the instruction "MOV IP, #000l0000B" will do it.
4. If both are activated at the same time, INT0 is serviced first since it has a higher priority. After INT0 is serviced, INTl is serviced, assuming that the external interrupts are edge-triggered and H-to-L transitions are latched. In the case of low-level triggered interrupts, if both are activated at the same time, the INTO is serviced first; then after the 8051 has finished servicing the INT0, it scans the INT0 and INTl pins again, and if the INTl pin is still high, it will be serviced.
5. We have an interrupt inside an interrupt, meaning that the lower-priority interrupt is put on hold and the higher one is serviced. After servicing this higher-priority interrupt, the 8051 resumes servicing the lower-priority ISR.
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