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Lecture Notes and Lecture Slides on "Digital Electronics - II (Revised) with Solutions to Problem sets" by Prof. Peter Y. K. Cheung sir


Digital Electronics - II (Revised @ spring 2013)
 by Prof. Peter Y. K. Cheung sir

 
Prof. Peter Y. K. Cheung
Professor of Digital Systems
Head, Department of Electrical & Electronic Engineering

Imperial College
OF SCIENCE, TECHNOLOGY AND MEDICINE
Room 912, Electrical & Electronic Engineering
Exhibition Road
London SW7 2BT, England
                                    Phone: +44 207 594 6263 
                                    Fax: +44 207 581 4419 
                                    Email: p.cheung@imperial.ac.uk
Aims & Objectives
The aims of the course are:
  • To enable you to analyse and synthesize small synchronous digital systems.
  • To give an understanding of factors that limit the performance of digital systems.
  • To give an understanding of how digital systems communicate with each other and with their external environment.
By the end of the course, you should be able to:
  • analyse the operation of synchronous digital systems
  • synthesize a synchronous digital system to meet a specification
  • determine the worst-case propagation delay of a combinational circuit
  • evaluate the performance of A/D and D/A conversion circuits
  • design arithmetic circuits to meet a specification and determine the propagation delay
  • design some digital circuits on real hardware
This course is supported by Terasic/Altera's DE0 board with a daughter board extension. Each student can sign out one board for the term from EEE Stores.
Please return the board by the end of the Spring term.




Textbooks
Digital Systems – Principles and Applications”, 9th Ed, R. J. Tocci and N. S. Widmer, Prentice Hall,
 "Digital Design: A Systems Approach", W.J. Dally and R. Curtis, Cambridge University Press, 


Lecture Notes

Introduction & Preliminaries
    Lecture 1  Basics & background
    Lecture 2  FPGAs, Design Flow & DE0 Board
    Lecture 3A  Verilog HDL - Part 1s
    Lecture 3B  Verilog HDL - Part 2
Interfacing Digital Systems
    Lecture 4  Synchronous bit-serial interfacing
    Lecture 5  Memory interfacing
    Lecture 6  FPGA Embedded Memory (R6.1, R6.2, R6.3, R6.4)
Interfacing with Analogue Systems
    Lecture 7  Digital-to-Analgue Conversion (R7.1)
    Lecture 8  Analogue-to-Digital Conversion
    Lecture 9  Practical Data Converters (R9.1, R9.2)
Synchronous State Machines & Control Circuits
    Lecture 10 Control Logic
    Lecture 11 Synchronous state machine analysis
    Lecture 12 Synchronous state machine design
    Lecture 13 State Machine in Verilog
Arithmetic Circuits

    Lecture 14 Adder Circuits







Tutorial Problem Sheets & Practical Exercises (FAQ page relating to DE0)

Tutorial Problems
Practical Exercises
Resources






DE0 & Cyclone III Resources

Quartus II Software v12.1 web-edition (Download page)
Quartus Tutorial Page (containing MANY tutorials, probably too many. Be selective!)
Getting Started with DE0 (PDF)
DE0 User's Manual (PDF)
Cyclone III Handbook (PDF)
FPGA & CPLD Architecture: A Tutorial by Brown and Rose (PDF)

Introduction to Quartus II (PDF)


Problem Classes Handouts
Problem Class 1 (21 Jan 2013)
Problem Class 2 (28 Jan 2013)
Problem Class 3 (4 Feb 2013)
Problem Class 4 (18 Feb 2013)

Problem Class 5 (11 Mar 2013)