Modeling and Synthesis of digital systems using Verilog and VHDL
Dr. R. James Duckworth, AK301, Tel: (508) 831-5204, email: email@example.com
Office hours: MTRF 10 to 11am (send email for other times)
This is an introductory course on Verilog and VHDL, two standard hardware description languages (HDLs), for students with no background or prior experience with HDLs. In this course we will examine some of the important features of Verilog and VHDL. The course will enable students to design, simulate, model and synthesize digital designs. The dataflow, structural, and behavioral modeling techniques will be discussed and related to how they are used to design combinational and sequential circuits. The use of test benches to exercise and verify the correctness of hardware models will also be described.
Course Projects: Course projects will involve the modeling and synthesis and testing using Xilinx tools. We will be targeting Xilinx FPGA and CPLDs. Students will need to purchase the NEXSYS3 FPGA development board for project assignments. (Other synthesis and simulation tools may be used if these are available to the students at their place of employment.) Students will have the choice of completing assignments in either Verilog or VHDL.