GATE
2015 ECE – Questions on Digital Circuits with Solutions
1. The circuit shown consists of JK flip flops, each with an active LOW
asynchronous reset. The counter corresponding to this circuit is ___________
a.
Mod – 5 binary UP counter
b.
Mod – 6 binary DOWN counter
c.
Mod – 5 binary DOWN counter
d.
Mod – 6 binary UP counter
2. In the circuit shown, D1, D2 and D3
are ideal and inputs E1, E2 and E3 are 0 volts
for logic’0’ and 10 volts for logic ‘1’. What logic gate does the circuit
represent?
a.
3 input OR gate
b.
3 input NOR gate
c.
3 input AND gate
d.
3 input XOR gate
3. A universal gate can implement any Boolean function by connecting
sufficient number of them appropriately. Three gates are shown.
Which one of the following
statements is TRUE?
a.
Gate 1 is universal gate
b.
Gate 2 is universal gate
c.
Gate 3 is universal gate
d.
None of the gates shown is universal gate
4. A three bit pseudo random number generator is shown. Initially the
value of output Y = Y2Y1Y0 is set to 111. The
value of output Y after three clock cycles is _________
a.
000
b.
001
c.
010
d.
100
5. An SR latch is implemented using TTL gates as shown in the figure.
The set and reset pulse inputs are provided using the push button switches. It
is observed that the circuit fails to work as desired. The SR latch can be made
functional by changing
a.
NOR gates to NAND gates
b.
Inverters to Buffers
c.
NOR gates to NAND gates and inverters to buffers
d.
5 volts to ground
6. Consider a four bit Digital to Analog converter. The analog value
corresponding to a digital signals of values 0000 and 0001 are 0 volts and
0.0625 volts respectively. The analog value (in volts) corresponding to the
digital signal 1111 is ______________
7. In a 8085 microprocessor, the shift registers which store the result
of an addition and the overflow bit are respectively
a.
B and F
b.
A and F
c.
H and F
d.
A and C
8. A 16 KB memory array is designed as a square with an aspect ratio of
one (number of rows is equal to the number of columns). The minimum number of
address lines needed for the row decoder is ______________
9. A 3 input majority gate is defined by the logic function M(a,b,c) =
ab + bc + ca. Which one of the following gate is represented by the function M(M’(a,b,c),M(a,b,c’),c)?
a.
3 input NAND gate
b.
3 input XOR gate
c.
3 input NOR gate
d.
3 input XNOR gate
10. The Boolean expression F(x,y,z) = x’yz’+xy’z’+xyz’+xyz converted
into canonical product of sum (POS) form is ___________
11. All the logic gates shown in the figure have a propagation delay of
20 ns. Let A=C=0 and B=1 until time t = 0. At t = 0, all the inputs flip (i.e.
A=C=1 and B=0) and remain in that state. For t>0, output z=1 for a duration
(in 20 ns) of____________
12. A Mod-N counter using a synchronous binary UP counter with
asynchronous clear input is shown in the figure. The value of N
is_______________
13. In the figure shown, the output Y is required to be Y = AB+C’D’. The
gates G1 and G2 must be _____
a.
NOR, OR
b.
OR, NAND
c.
NAND, OR
d.
AND, NAND
14. In an 8085 microprocessor, which one of the following instructions
changes the content of the accumulator?
a.
MOV B,M
b.
PCHL
c.
RNZ
d.
SBI BEH .
15. A function of Boolean variables X,Y and Z is expressed in terms of
the min-terms as F(X,Y,Z) = ∑m(1,2,5,6,7). Which one of the product of sums given below is equal
to the given function?
16. The figure shows a binary counter with synchronous clear input. With
the decoding logic shown, the counter works as a _______________
a.
Mod – 2 counter
b.
Mod – 4 counter
c.
Mod – 5 counter
d.
Mod – 6 counter
17. Problem on Design of 1 to 8 De-multiplexer using two 2 to 4 decoders
with extra logic gates.
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