SECTION 14.1: SEMICONDUCTOR MEMORY
1. The speed of semiconductor memory is in the range of
(a) microseconds (b) milliseconds
(c) nanoseconds (d) picoseconds
2. Find the organization and chip capacity for each ROM with the indicated number of address and data pins.
(a) 14 address, 8 data (b) 16 address, 8 data (c) 12 address, 8 data
3. Find the organization and chip capacity for each RAM with the indicated number of address and data pins.
(a) 11 address, 1 data SRAM (b) 13 address, 4 data SRAM
(c) 17 address, 8 data SRAM (d) 8 address, 4 data DRAM
(e) 9 address, 1 data DRAM (f) 9 address, 4 data DRAM
4. Find the capacity and number of pins set aside for address and data for memory chips with the following organizations.
(a) 16Kx4 SRAM (b) 32Kx8 EPROM (c) lMxl DRAM
(d) 256Kx4 SRAM (e) 64Kx8 EEPROM (f) 1Mx4 DRAM
5. Which of the following is (are) volatile memory?
(a) EEPROM (b) SRAM (c) DRAM (d) NV-RAM
2. (a) 16Kx8, 128K bits ( b) 64Kx8, 512K (c) 4Kx8, 32K
3. (a) 2Kxl, 2K bits (b) 8Kx4, 32K (c) 128Kx8, lM
(d) 64Kx4, 256K (e) 256Kxl, 256K (f) 256Kx4, lM
4. (a) 64K bits, 14 address, and 4 data (b) 256K, 15 address, and 8 data
(c) lM, 10 address, and 1 data (d) lM, 18 address, and 4 data
(e) 512K, 16 address, and 8 data (f) 4M, 10 address, and 4 data
5. b, c
SECTION 14.2: MEMORY ADDRESS DECODING
1. A given memory block uses addresses 4000H - 7FFFH. How many K bytes is this memory block?
2. The 74138 is a(n) ______ by ______ decoder.
3. In the 74138 give the status of G2A and G2B for the chip to be enabled.
4. In the 74138 give the status of Gl for the chip to be enabled.
5. In Example 14-6, what is the range of addresses assigned to Y5?
1. 16K bytes
2. 3, 8
3. Both must be low.
4. Gl must be high.
5. 5000H- 5FFFH
SECTION 14.3: 8031/51 INTERFACING WITH EXTERNAL ROM
1. If EA= GND, indicate from what source the program code is fetched.
2. If EA = Vcc' indicate from what source the program code is fetched.
3. Which port of the 8051 is used for address/ data multiplexing?
4. Which port of the 8051 provides D0 - D7?
5. Which port of the 8051 provides A0 - A7?
6. Which port of the 8051 provides A8 - A15?
7. True or false. In accessing externally stored program code, the PSEN signal is always activated.
1. From external ROM (that is off-chip)
2. From internal ROM (that is on-chip)
SECTION 14.4: 8051 DATA MEMORY SPACE
1. The 8051 has a total of _______ bytes of memory space for both program code and data.
2. All the data memory space of the 8051 is ___________ (internal, external).
3. True or false. In the 8051, program code must be read-only memory.
4. True or false. In the 8051, data memory can be read or write memory.
5. Explain the role of pins PSEN, RD, and WR in accessing external memory.
6. True or false. Every 8051 chip comes with lKB of SRAM.
7. True or false. Upon reset, access to the lKB SRAM of the DS89C4x0 is blocked.
5. Only PSEN is used to access external ROM containing program code, but when accessing external data memory we must use RD and WR signals. In other words, RD and WR are only for external data memory and are never used for external program ROM.